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12:00am • Keynote: RISC-V Right here. Right now. - Calista Redmond, CEO, RISC-V International
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12:20am • Keynote: RISC-V in China - Dr. Guangnan Ni, Academician of the Chinese Academy of Engineering
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12:40am • Keynote: RISC-V in Academia and Education - Stefan Wallentowitz, Professor, Munich University of Applied Sciences & Calista Redmond, CEO, RISC-V International
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12:55am • Keynote: RISC-V - A User's Perspective - Loic Lietar, CEO GreenWaves Technologies SAS
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1:05am • Break
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1:05am • Ask the Expert Session with Akira Tsukamoto, Senior Research Scientist, The National Institute of Advanced Industrial Science and Technology (AIST)
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1:45am • Portable Implementation of GlobalPlatform API for TEE - Kenta Nakajima & Kuniyasu Suzaki, Technology Research Association of Secure IoT Edge Application Based on RISC-V Open Architecture (TRASIO)
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1:45am • Vector Compliance Testing for RISC-V - Hideki Sugimoto & Koji Adachi, NSITEXE Inc.
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2:20am • Andes RISC-V Processors for Control and Data Paths - Charlie Su, Andes Technology Corporation
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2:20am • Nutshell: A Linux-Compatible RISC-V Processor Designed by Undergraduates - Huaqiang Wang, University of Chinese Academy of Sciences
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2:55am • TEEP (Trusted Execution Environment Provisioning) on RISC-V - Akira Tsukamoto & Kuniyasu Suzaki, The National Institute of Advanced Industrial Science and Technology (AIST)
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2:55am • PicoRio: An Open-Source, RISC-V Small-Board Computer To Elevate The RISC-V Software Ecosystem - Zhangxi Tan, RIOS Lab
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3:25am • Ask the Expert Session with Wei Fu, Senior Software Engineer, Red Hat Software (Beijing) Co.,Ltd.
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3:25am • Break
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3:55am • CloudBEAR RISC-V Processor IP Product Line - Alexander Kozlov, CloudBEAR
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3:55am • Support TVM QNN Flow on RISC-V with SIMD Computation - Yi-Ru Chen & Jenq Kuen Lee, National Tsing Hua University, Taiwan
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4:10am • Optimize Openblas by RISC-V "V" Vector Extension - Xianyi Zhang, PerfXLab
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4:30am • Software Development for 64-Bit RISC-V Processor Verification - Sreenadh S & Sangeetha N., Center for Development of Advanced Computing, India
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4:30am • An Introduction to RISC-V Vector Programming with C Intrinsics - Chih-Mao Chen, Andes Technology
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4:45am • ProtoCPU: Modelling an In-Order RISC-V Core in gem5 - Anuj Justus Rajappa, IIT Madras
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5:05am • Using Formal to Vaccinate RISC-V Designs Against Catastrophic Bugs - Dr. Ashish Darbari, AXIOMISE
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5:35am • Break
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5:35am • Ask the Expert Session with Florian Wohlrab, RISC-V Ambassador and Head of Sales EMEA & Japan, Andes Technology
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6:05am • Optimizing RISC-V Custom Instructions with Software Driven Analysis and Profiling - Duncan Graham & Simon Davidmann, Imperas Software
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6:05am • BM-310 Small and Efficient MCU Core - Alexander Kozlov, CloudBEAR
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6:40am • Semidynamics New Family of High Bandwidth Vector-Capable Cores - Roger Espasa, SemiDynamics
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6:40am • Trusted Execution State: An Extension for Lightweight Secure Function Calling - Mark Hill, Huawei Technologies R&D (UK) Ltd
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7:10am • Ask the Expert Session with Drew Fusitni, Linux Developer and Hardware Designer, and Olof Kindgren, Digital Design Engineer, Open Source Silicon expert, and RISC-V Ambassador, Qamcom
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7:10am • Break
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8:00am • Keynote: Krste Asanovic, Chairman of the Board, RISC-V International
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8:25am • Keynote: EPI, The European Approach for Exascale ages. The Road Toward Sovereignty - Jean-Marc Denis, Chair of the Board, European Processor Initiative
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8:50am • Keynote: Chips Alliance: The Open Source Hardware Roadmap - Zvonimir Bandic, Chairman, CHIPS Alliance & Sr Director, Western Digital Corporation
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9:05am • Keynote: NVIDIA’s secure RISC-V processor - Frans Sijstermans & Joe Xie, NVIDIA
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9:20am • Break
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9:20am • Ask the Expert Session with Krste Asanovic, Chairman, and Dave Patterson, Vice Chair, RISC-V International
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9:45am • Riscof - A Risc-V Compliance Framework and More - Neel Gala, InCore Semiconductors
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9:45am • The Case for RISC-V in Space - Gianluca Furano, European Space Agency
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10:00am • Noel-V: A New High-Performance RISC-V Processor Family - Johan Klockars & Alen Bardizbanyan, Cobham Gaisler AB
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10:20am • Verifying All the Flexibility of RISC-V within SoC DV Test Plans - Simon Davidmann & Lee Moore, Imperas Software
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10:20am • Cloud-based Verification of Open Source RISC-V Cores Using the Metrics Cloud Platform and Codasip SweRV Support Package - Roddy Urquhart, Codasip & Dan Ganousis, Metrics Design Automation
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10:55am • RISC-V True Random Number Generation: Probably Too Important to be Left to Chance - Markku-Juhani O. Saarinen, PQShield Ltd.
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11:25am • Break
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11:25am • Ask the Expert Session with Mark I Himelstein, RISC-V CTO, and Stephano Cetola, Technical Program Manager, RISC-V International
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12:10pm • Stay Ahead with the Latest Advances in RISC-V Development Tools - Shawn Prestridge, IAR Systems
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12:10pm • Where Is the 32-Bit Glibc Port? - Alistair Francis, Western Digital
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12:45pm • An Automated Scalable RISC-V Cache Coherency Verification Project - Adnan Hamid, Breker Verification Systems, Inc.
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1:20pm • CORE-V Verification Test Bench – Commercial Quality Verification of Open-Source RISC-V Cores - Rick O'Connor, OpenHW Group; Simon Davidmann, Imperas; Aimee Sutton, Metrics
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1:20pm • Unlocking Javascript: V8 on RISC-V - Peng Wu & Brice Dobry, Futurewei Technologies
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1:50pm • Break
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1:50pm • Ask the Expert Session with Carlos Eduardo de Paula, Cloud Architect, Red Hat
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2:20pm • Code Size Compiler Optimizations and Techniques for Embedded Systems - Aditya Kumar, Facebook
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2:55pm • RVfpga: Using A Commercial RISC-V Processor to Teach Computer Architecture for the Next Generation of Engineers and Computer Scientists - Sarah L. Harris, University of Nevada, Las Vegas & Daniel A. Chaver Martinez, University Complutense of Madrid
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3:10pm • Omnixtend Boot Protocol and Coherent Scaleout - Dejan Vucinic, Western Digital Corporation
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3:30pm • Ask the Expert Session with Allen Baum, Senior Adult in the Room, Esperanto Technologies
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3:30pm • Break
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4:00pm • Keynote: The First Decade of RISC-V: A Worldwide Phenomenon - David Patterson, Vice Chair, RISC-V International
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4:25pm • Keynote: An Investor Perspective on RISC-V, The Opportunities and Challenges Ahead - Guru Chahal, Partner, Lightspeed Venture Partners
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4:50pm • Keynote: Information Revolution, Chips, and Openness - Shahin Khan, Founding Partner & Analyst, OrionX.net
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5:05pm • Keynote: Closing Remarks - Calista Redmond, CEO, RISC-V International
