RISC-V Global Forum 2020 has ended

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RISC-V Global Forum 2020

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12:00am PDT

Keynote: RISC-V Right here. Right now. - Calista Redmond, CEO, RISC-V International MeetingPlay

12:20am PDT

Keynote: RISC-V in China - Dr. Guangnan Ni, Academician of the Chinese Academy of Engineering MeetingPlay

12:40am PDT

Keynote: RISC-V in Academia and Education - Stefan Wallentowitz, Professor, Munich University of Applied Sciences & Calista Redmond, CEO, RISC-V International MeetingPlay

12:55am PDT

Keynote: RISC-V - A User's Perspective - Loic Lietar, CEO GreenWaves Technologies SAS MeetingPlay

1:05am PDT

Ask the Expert Session with Akira Tsukamoto, Senior Research Scientist, The National Institute of Advanced Industrial Science and Technology (AIST) MeetingPlay Break MeetingPlay

1:45am PDT

Vector Compliance Testing for RISC-V - Hideki Sugimoto & Koji Adachi, NSITEXE Inc. MeetingPlay Portable Implementation of GlobalPlatform API for TEE - Kenta Nakajima & Kuniyasu Suzaki, Technology Research Association of Secure IoT Edge Application Based on RISC-V Open Architecture (TRASIO) MeetingPlay

2:20am PDT

Nutshell: A Linux-Compatible RISC-V Processor Designed by Undergraduates - Huaqiang Wang, University of Chinese Academy of Sciences MeetingPlay Andes RISC-V Processors for Control and Data Paths - Charlie Su, Andes Technology Corporation MeetingPlay

2:55am PDT

TEEP (Trusted Execution Environment Provisioning) on RISC-V - Akira Tsukamoto & Kuniyasu Suzaki, The National Institute of Advanced Industrial Science and Technology (AIST) MeetingPlay PicoRio: An Open-Source, RISC-V Small-Board Computer To Elevate The RISC-V Software Ecosystem - Zhangxi Tan, RIOS Lab MeetingPlay

3:25am PDT

Ask the Expert Session with Wei Fu, Senior Software Engineer, Red Hat Software (Beijing) Co.,Ltd. MeetingPlay Break MeetingPlay

3:55am PDT

Support TVM QNN Flow on RISC-V with SIMD Computation - Yi-Ru Chen & Jenq Kuen Lee, National Tsing Hua University, Taiwan MeetingPlay CloudBEAR RISC-V Processor IP Product Line - Alexander Kozlov, CloudBEAR MeetingPlay

4:10am PDT

Optimize Openblas by RISC-V "V" Vector Extension - Xianyi Zhang, PerfXLab MeetingPlay

4:30am PDT

An Introduction to RISC-V Vector Programming with C Intrinsics - Chih-Mao Chen, Andes Technology MeetingPlay Software Development for 64-Bit RISC-V Processor Verification - Sreenadh S & Sangeetha N., Center for Development of Advanced Computing, India MeetingPlay

4:45am PDT

ProtoCPU: Modelling an In-Order RISC-V Core in gem5 - Anuj Justus Rajappa, IIT Madras MeetingPlay

5:05am PDT

Using Formal to Vaccinate RISC-V Designs Against Catastrophic Bugs - Dr. Ashish Darbari, AXIOMISE MeetingPlay

5:35am PDT

Ask the Expert Session with Florian Wohlrab, RISC-V Ambassador and Head of Sales EMEA & Japan, Andes Technology MeetingPlay Break MeetingPlay

6:05am PDT

BM-310 Small and Efficient MCU Core - Alexander Kozlov, CloudBEAR MeetingPlay Optimizing RISC-V Custom Instructions with Software Driven Analysis and Profiling - Duncan Graham & Simon Davidmann, Imperas Software MeetingPlay

6:40am PDT

Semidynamics New Family of High Bandwidth Vector-Capable Cores - Roger Espasa, SemiDynamics MeetingPlay Trusted Execution State: An Extension for Lightweight Secure Function Calling - Mark Hill, Huawei Technologies R&D (UK) Ltd MeetingPlay

7:10am PDT

Ask the Expert Session with Drew Fusitni, Linux Developer and Hardware Designer, and Olof Kindgren, Digital Design Engineer, Open Source Silicon expert, and RISC-V Ambassador, Qamcom MeetingPlay Break MeetingPlay

8:00am PDT

Keynote: Krste Asanovic, Chairman of the Board, RISC-V International MeetingPlay

8:25am PDT

Keynote: EPI, The European Approach for Exascale ages. The Road Toward Sovereignty - Jean-Marc Denis, Chair of the Board, European Processor Initiative MeetingPlay

8:50am PDT

Keynote: Chips Alliance: The Open Source Hardware Roadmap - Zvonimir Bandic, Chairman, CHIPS Alliance & Sr Director, Western Digital Corporation MeetingPlay

9:05am PDT

Keynote: NVIDIA’s secure RISC-V processor - Frans Sijstermans & Joe Xie, NVIDIA MeetingPlay

9:20am PDT

Ask the Expert Session with Krste Asanovic, Chairman, and Dave Patterson, Vice Chair, RISC-V International MeetingPlay Break MeetingPlay

9:45am PDT

The Case for RISC-V in Space - Gianluca Furano, European Space Agency MeetingPlay Riscof - A Risc-V Compliance Framework and More - Neel Gala, InCore Semiconductors MeetingPlay

10:00am PDT

Noel-V: A New High-Performance RISC-V Processor Family - Johan Klockars & Alen Bardizbanyan, Cobham Gaisler AB MeetingPlay

10:20am PDT

Cloud-based Verification of Open Source RISC-V Cores Using the Metrics Cloud Platform and Codasip SweRV Support Package - Roddy Urquhart, Codasip & Dan Ganousis, Metrics Design Automation MeetingPlay Verifying All the Flexibility of RISC-V within SoC DV Test Plans - Simon Davidmann & Lee Moore, Imperas Software MeetingPlay

10:55am PDT

RISC-V True Random Number Generation: Probably Too Important to be Left to Chance - Markku-Juhani O. Saarinen, PQShield Ltd. MeetingPlay

11:25am PDT

Ask the Expert Session with Mark I Himelstein, RISC-V CTO, and Stephano Cetola, Technical Program Manager, RISC-V International MeetingPlay Break MeetingPlay

12:10pm PDT

Stay Ahead with the Latest Advances in RISC-V Development Tools - Shawn Prestridge, IAR Systems MeetingPlay Where Is the 32-Bit Glibc Port? - Alistair Francis, Western Digital MeetingPlay

12:45pm PDT

An Automated Scalable RISC-V Cache Coherency Verification Project - Adnan Hamid, Breker Verification Systems, Inc. MeetingPlay

1:20pm PDT

CORE-V Verification Test Bench – Commercial Quality Verification of Open-Source RISC-V Cores - Rick O'Connor, OpenHW Group; Simon Davidmann, Imperas; Aimee Sutton, Metrics MeetingPlay Unlocking Javascript: V8 on RISC-V - Peng Wu & Brice Dobry, Futurewei Technologies MeetingPlay

1:50pm PDT

Ask the Expert Session with Carlos Eduardo de Paula, Cloud Architect, Red Hat MeetingPlay Break MeetingPlay

2:20pm PDT

Code Size Compiler Optimizations and Techniques for Embedded Systems - Aditya Kumar, Facebook MeetingPlay

2:55pm PDT

RVfpga: Using A Commercial RISC-V Processor to Teach Computer Architecture for the Next Generation of Engineers and Computer Scientists - Sarah L. Harris, University of Nevada, Las Vegas & Daniel A. Chaver Martinez... MeetingPlay

3:10pm PDT

Omnixtend Boot Protocol and Coherent Scaleout - Dejan Vucinic, Western Digital Corporation MeetingPlay

3:30pm PDT

Ask the Expert Session with Allen Baum, Senior Adult in the Room, Esperanto Technologies MeetingPlay Break MeetingPlay

4:00pm PDT

Keynote: The First Decade of RISC-V: A Worldwide Phenomenon - David Patterson, Vice Chair, RISC-V International MeetingPlay

4:25pm PDT

Keynote: An Investor Perspective on RISC-V, The Opportunities and Challenges Ahead - Guru Chahal, Partner, Lightspeed Venture Partners MeetingPlay

4:50pm PDT

Keynote: Information Revolution, Chips, and Openness - Shahin Khan, Founding Partner & Analyst, OrionX.net MeetingPlay

5:05pm PDT

Keynote: Closing Remarks - Calista Redmond, CEO, RISC-V International MeetingPlay