RISC-V Global Forum 2020: Full Schedule

12:00am PDT

Keynote: RISC-V Right here. Right now. - Calista Redmond, CEO, RISC-V International

RISC-V is tearing down barriers to entry and driving an open and collaborative future for the semiconductor industry. Join my talk to dive into the RISC-V realm of disruptive technology, unconstrained opportunity, and engaged community. I’ll share the progress we’ve made, the programs in motion, and our vision for the future of computing.

Speakers

Calista Redmond

CEO, RISC-V International, RISC-V International

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of... Read More →

Thursday September 3, 2020 12:00am - 12:15am PDT
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Keynote

12:20am PDT

Keynote: RISC-V in China - Dr. Guangnan Ni, Academician of the Chinese Academy of Engineering

In the Oct 2019 edition of the Economist Magazine, there was an article about open-source computing, which states: “Open-source software was a prerequisite for the smartphone boom that has taken place over the past decade. Open-source hardware, such as RISC-V, may lead to a similar expansion of other devices in the decade to come.”

RISC-V, as the foundation of open source hardware, has gained tremendous attentions in China. In this talk, Dr. Guangnang Ni, member of Chinese Academy of Engineering and the chair of China RISC-V Alliance (CRVA), will briefly introduce the status of RISC-V in China.

Speakers

Dr. Guangnan Ni

Academician, Chinese Academy of Engineering

Thursday September 3, 2020 12:20am - 12:35am PDT
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Keynote

12:40am PDT

Keynote: RISC-V in Academia and Education - Stefan Wallentowitz, Professor, Munich University of Applied Sciences & Calista Redmond, CEO, RISC-V International

In this keynote, Calista Redmond and Stefan Wallentowitz have a dialogue about RISC-V in academia and education. They discuss challenges and opportunities of RISC-V in research and teaching and give an outlook to goals of the revived special interest group "Academia & Education".

Speakers

Calista Redmond

CEO, RISC-V International, RISC-V International

Stefan Wallentowitz

Professor, Munich University of Applied Sciences

Stefan is a professor at Munich University of Applied Sciences. He is a long term advocate and active member of the open source silicon community, most prominent in his role as director of the Free and Open Source Silicon Foundation (FOSSi Foundation). He has been active in various... Read More →

Thursday September 3, 2020 12:40am - 12:50am PDT
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Keynote

12:55am PDT

Keynote: RISC-V - A User's Perspective - Loic Lietar, CEO GreenWaves Technologies SAS

Speakers

Loic Lietar

CEO, GreenWaves Technologies SAS

Loïc is a co-founder and the CEO of GreenWaves Technologies, a fabless semiconductor start-up developing GAP8, an IoT application processor with a unique energy efficiency that enables new to world autonomous content understanding applications (image, sound and motion). Prior to... Read More →

Thursday September 3, 2020 12:55am - 1:05am PDT
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Keynote

1:05am PDT

Ask the Expert Session with Akira Tsukamoto, Senior Research Scientist, The National Institute of Advanced Industrial Science and Technology (AIST)

This is your chance to chat directly with RISC-V leaders and ambassadors to get all of your questions answered. Have a technical question? Curious on a career trajectory? Or simply want some RISC-V tips? This is the place to get this and more answered, as our experts sit down for our ‘Ask the Expert’ Sessions.

Speakers

Akira Tsukamoto

Senior Researcher, AIST (The National Institute of Advanced Industrial Science and Technology Japan)

Akira Tsukamoto works at AIST (The National Institute of Advanced Industrial Science and Technology Japan). His main focusing area is on both software engineering and hardware engineering on network, operating system and system security. He is enthusiastic on any kind of technical... Read More →

Thursday September 3, 2020 1:05am - 1:45am PDT
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Ask the Expert

1:05am PDT

Break

Thursday September 3, 2020 1:05am - 1:45am PDT
MeetingPlay

Break

1:45am PDT

Vector Compliance Testing for RISC-V - Hideki Sugimoto & Koji Adachi, NSITEXE Inc.

The first step to testing a RISC-V vector instruction implementation is to test compliance to the specification. To do this requires both compliance tests and a reference model. NSITEXE, with its Data Flow Processor (DFP) IP block, required such testing for its implementation of the vector engine. The Imperas RISC-V ISS, riscvOVPsim, is in use as the reference model for the RISC-V Compliance Test Suite (CTS). Imperas has developed a Directed Compliance Test Generator, which achieves over 95% functional instruction coverage with those tests generated. Using the Vector CTS for the NSITEXE configuration has enabled confirmation of compliance with v0.8 of the RISC-V vector specification. This paper will discuss the NSITEXE DFP vector engine implementation, the generation of the Vector Compliance Tests for the NSITEXE configuration and the results of those tests including coverage data.

Speakers

Hideki Sugimoto

CTO, NSITEXE Inc.

Hideki Sugimoto is currently CTO of NSITEXE, Inc., a 100% subsidiary of DENSO Corporation, which is working to innovate embedded SoC architecture to makes it more generic, flexible and scalable. He has over 25 years of experience in NEC as a processor architect, designer and also... Read More →

Koji Adachi

Manager, NSITEXE, Inc.

Koji Adachi has more than 15 years of experience as a CPU architect and designer for embedded applications and is currently a CPU architect at NSITEXE, Inc. Previously, he worked on CPU ISA (Virtualization, Multithreading) and micro architecture design for Automotive MCUs. He also... Read More →

RV GF VectorCTS NSITEXE pdf

Thursday September 3, 2020 1:45am - 2:15am PDT
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Industry

1:45am PDT

Portable Implementation of GlobalPlatform API for TEE - Kenta Nakajima & Kuniyasu Suzaki, Technology Research Association of Secure IoT Edge Application Based on RISC-V Open Architecture (TRASIO)

TEE (Trusted Execution Environment) is a CPU feature that offers an isolated environment for critical processing. RISC-V has some TEE implementations, i.e., Keystone, Sanctum, etc. However, each CPU offers an original programming model and the portability is not kept. GlobalPlatform (GP) offers TEE Internal APIs, but it is used on ARM TrustZone mainly. Most implementations are on a Trusted OS and cannot be port to another TEE easily.

We implement GP TEE APIs as a portable library. Most APIs are independent of CPU architecture, but some APIs are not (e.g., Secure Storage, Secure Timer) and implemented for each architecture. The current library is available for RISC-V Keystone and Intel SGX, and the performance was measured on both architectures (Pentium and SiFive Unleashed). The results showed that most are the same but the low performance of secure storage on Keystone.

Speakers

Kuniyasu Suzaki

Senior Researcher, National Institute of Advanced Industrial Science and Technology (AIST)

Kuniyasu Suzaki works at National Institute of Advanced Industrial Science and Technology (AIST). He got his Bachelor and Master (Engineering) from Tokyo University of Agriculture and Technology (TUAT) and Ph.D (Information Science and Technology) from the University of Tokyo. His... Read More →

Kenta Nakajima

Researcher, TRASIO

Kenta Nakajima works at Technology Research Association of Secure IoT Edge application based on RISC-V Open architecture(TRASIO). His main focusing area is software engineering on operating system, system security and software automation. He is interereted in how the Linux OS and... Read More →

Riscv GlobalForum Portable Implementation of GlobalPlatform API for TEE pdf

Thursday September 3, 2020 1:45am - 2:15am PDT
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Technical

2:20am PDT

Nutshell: A Linux-Compatible RISC-V Processor Designed by Undergraduates - Huaqiang Wang, University of Chinese Academy of Sciences

NutShell is an in-order linux-compatible RISC-V processor designed by five undergraduate students from University of Chinese Academy of Sciences. This processor supports RV64IMAC instruction extension and SV39 virtual-memory system. It has been typed out using SMIC 110nm process technology. The test chip can successfully boot the Linux kernel.

A cycle-level differential testing framework is used is used during development, in which an emulator (NEMU) runs side by side with the processor being tested. With the help of that framework, the develop team managed to boot linux on NutShell in a short period of time.

This talk will introduce the development process of this chip from the perspective of undergraduate students participating in the project. Experience of developing with Chisel and debugging with the differential testing framework will also be shared.

Speakers

Huaqiang Wang

Student, University of Chinese Academy of Sciences

2016 to 2020: Study for bachelor degree of computer science in University of Chinese Academy of Sciences.No previous speaking experience.

RISC V Global Forum 2020 HuaqiangWang NutShell pdf

Thursday September 3, 2020 2:20am - 2:50am PDT
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Industry

2:20am PDT

Andes RISC-V Processors for Control and Data Paths - Charlie Su, Andes Technology Corporation

Andes V5 RISC-V processor IP solutions have been adopted by a wide range of SoCs: from tiny MCUs for consumer products, to chips for enterprise and datacenter products. For single-processor SoC, Andes DSP or vector processor can cover both control and data processing. For advanced SoC using multiple processors, some V5 cores tackle data-intensive computations while others handles control paths.

In this talk, Dr. Charlie Su will give an overview of Andes processor solutions and control/data path processing in applications. He will then use Andes processors as examples to show how RISC-V processors and their features can provide efficient control/data path processing. Charlie will also introduce Andes Custom Extension™ (ACE) framework and illustrate how it automates RISC-V custom instruction extensions to further accelerate control/data path processing while maintaining programmability.

Speakers

Charlie Su

President and CTO, Andes Technology

Dr. Charlie Su, Co-founder, CTO and President of Andes Technology, has overseen engineering and marketing since the company started in 2005. Under his leadership, Andes developed processor IP solutions based on its own ISA before joining the RISC-V Foundation as a founding member... Read More →

200903 CharlieSu Andes RISCV for Control n Data Paths pdf

Thursday September 3, 2020 2:20am - 2:50am PDT
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Technical

2:55am PDT

TEEP (Trusted Execution Environment Provisioning) on RISC-V - Akira Tsukamoto & Kuniyasu Suzaki, The National Institute of Advanced Industrial Science and Technology (AIST)

IETF is defining Trusted Execution Environment Provisioning (TEEP) protocol to remotely install/update/delete of TA (Trusted Application) in TEE (Trusted Execution Environment) which provides hardware isolated security in CPU. TEEP is designed to be generic among different CPU architectures; however primary activity is on Intel and ARM only. Therefore, our team is implementing TEEP on RISC-V.

TEEP consists of 3 major software components; “TEEP Broker” on the OS, “TEEP Agent” in the TEE, and “Trusted Application Manager (TAM)” as a remote server. These components manage certificates for authenticating TEE and TAM, and code signing of TA. All of the certificates are based on PKI management. The challenges of having TEEP on RISC-V is how to minimize required features, such as HTTP, Concise Binary Object Representation (CBOR) parser, inside TEE while keeping the portability of existing TA.

Speakers

Akira Tsukamoto

Senior Researcher, AIST (The National Institute of Advanced Industrial Science and Technology Japan)

Kuniyasu Suzaki

Senior Researcher, National Institute of Advanced Industrial Science and Technology (AIST)

RISC VGlobalPlatform TEEP 2 (1) pdf

RISC VGlobalPlatform TEEP 2 pdf

Thursday September 3, 2020 2:55am - 3:25am PDT
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Industry

2:55am PDT

PicoRio: An Open-Source, RISC-V Small-Board Computer To Elevate The RISC-V Software Ecosystem - Zhangxi Tan, RIOS Lab

PicoRio is an open-source project stewarded by the RISC-V International Open Source (RIOS) laboratory—rioslab.org—a nonprofit research lab at Tsinghua-Berkeley Shenzhen Institute (TBSI). The RIOS Lab uses collaborative engineering from both academia and industry to elevate the RISC-V software and hardware ecosystem. In PicoRio, we create an open, affordable, Linux-capable RISC-V hardware platform to aid software developers in porting many modern programs that require Javascript or GPUs. PicoRio will build upon high-quality IPs and software components from expert industry engineers and academic researchers. PicoRio is not proprietary to any specific vendor and platform, and will have complete documentation that can help people to build quality products in a short amount of time. Our plan is to ship PicoRio 1.0 in 1H2021.

Speakers

Zhangxi Tan

Co-director, RIOS Lab

Dr. Zhangxi Tan is a co-director of the RISC-V International Open-source Laboratory (RIOS), leading open-source IP and software development that helps the RISC-V ecosystem world-class. Dr. Tan is an adjunct professor at Tsinghua-Berkeley Shenzhen Institute (TBSI). He received his... Read More →

Thursday September 3, 2020 2:55am - 3:25am PDT
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Technical

3:25am PDT

Ask the Expert Session with Wei Fu, Senior Software Engineer, Red Hat Software (Beijing) Co.,Ltd.

Speakers

Wei Fu

Senior Software Engineer, Red Hat

Linux kernel/distro developer with Embedded/Enterprise experience on Linux kernel/driver ,BSP, system porting, CI-loop and testing. Also have some experience on Firmware (U-boot/arm-TF/UEFI/ACPI/GRUB). Currently studying Linux distro,like Fedora/RHEL/CentOS on RISC-V. Also interested... Read More →

Thursday September 3, 2020 3:25am - 3:55am PDT
MeetingPlay

Ask the Expert

3:25am PDT

Break

Thursday September 3, 2020 3:25am - 3:55am PDT
MeetingPlay

Break

3:55am PDT

Support TVM QNN Flow on RISC-V with SIMD Computation - Yi-Ru Chen & Jenq Kuen Lee, National Tsing Hua University, Taiwan

The inference phase with low power and memory limited environments is critical for deploying neural network models on edge devices. One possible approach is adopting the quantization technique to represent activations and weights in lower bits. In this work, we present the efficiently inference quantized models by supporting TVM QNN flow with RISC-V SIMD computations. As RISC-V supports both Superword SIMD and Subword SIMD, we compile models by TVM and replace the computation kernel with designated LLVM intrinsic functions for mapping with RISC-V favorable SIMD instructions. Experiments shows 1.79-7.58x reduction of instruction count compared quantized model with FP32 implementation. The accuracy loss is acceptable by evaluating on 1k images. The benchmark including MobileNet and Inception series. All experiments are executed on Spike with RISC-V SIMD supports.

Speakers

Yi-Ru, Chen

Graduate student, National Tsing Hua University, Taiwan

Jenq-Kuen Lee

Professor, National Tsing-Hua University, Taiwan

Jenq-Kuen Lee received the B.S. degree in computer science from National Taiwan University in 1984. He received the M.S. and Ph.D. degrees in 1991 and 1992, respectively, in computer science from Indiana University. He is now a professor at National Tsing-Hua University, Taiwan, where... Read More →

RISC V GlobalForum Support TVM QNN Flow on RISC V with SIMD Computation pdf

Thursday September 3, 2020 3:55am - 4:10am PDT
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Technical

3:55am PDT

CloudBEAR RISC-V Processor IP Product Line - Alexander Kozlov, CloudBEAR

CloudBEAR's commercial RISC-V processor IP portfolio and feature set are increasing serving growing demands for mature RISC-V solutions. CloudBEAR BM, BR, BI series are covering a wide range of applications from small low-power microcontrollers to high-performance accelerators and Linux capable devices.
In this talk, we will give an overview of existing processor solutions and describe
newest developed features enriching company's offer.

Speakers

Alexander Kozlov

CTO, CloudBEAR

Alexander Kozlov is co-founder and CTO of CloudBEAR. Alexander has more than 15 years’ experience in developing software/hardware solutions based on FPGA and ASIC design. He has Master degree an EECS from Saint-Petersburg State Polytechnical University. He started his carrier as... Read More →

Thursday September 3, 2020 3:55am - 4:25am PDT
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Industry

4:10am PDT

Optimize Openblas by RISC-V "V" Vector Extension - Xianyi Zhang, PerfXLab

OpenBLAS is an open source BLAS (Basic Linear Algebra Subprograms) implementation, which is the building block of dense matrix software stack. Currently, OpenBLAS is used by high performance computing applications, and machine learning / deep learning applications.

The speaker introduces the work of porting OpenBLAS on RISC-V ISA. Furthermore, they presents how to optimize the software performance by RISC-V "V" Vector Extension, including GEMM (matrix multiplication), the BLAS level 3 function, and axpy, the BLAS level 1 function. Then, the speaker gives the performance benefit on XuanTie C910 RISC-V processor.

Speakers

Xianyi Zhang

CEO, PerfXLab

Xianyi get his Ph.D. degree from Chinese Academy of Sciences. His research interests focus on high performance computational software and matrix computing libraries. He leads an open source matrix computing library, OpenBLAS, from 2010. In 2015 and 2016, Xianyi do postdoc research... Read More →

OpenBLAS xianyi RISC V GlobalForum2020 2 pdf

Thursday September 3, 2020 4:10am - 4:25am PDT
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Technical

4:30am PDT

An Introduction to RISC-V Vector Programming with C Intrinsics - Chih-Mao Chen, Andes Technology

The "V" ISA extension for vector processing has been proposed to RISC-V to exploit data parallelism in domains such as machine learning and high-performance computing applications. In contrast to traditional SIMD processors with fixed-length vectors, the RISC-V vector extension defines a vector-length agnostic architecture where work is vectorized independently of a vector length that can be discovered at run-time. This is a departure from existing SIMD frameworks where the vector lengths are known statically, and a new intrinsic interface that takes advantage of scalable nature of RISC-V vectors is being developed by the community. This talk will provide an overview of the vector extension and how to program the vector processor, using Andes NX27V as an example, with C-level scalable vector types and intrinsic functions, as well as design choices and future evolution of the API.

Speakers

Chih-Mao Chen

Toolchain Engineer, Andes Technology

Chih-Mao Chen is a software developer at Andes Technology, where he is responsible at developing RISC-V toolchain based on the LLVM compiler infrastructure.

rvv intrinsics global forum pdf

Thursday September 3, 2020 4:30am - 4:45am PDT
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Technical

4:30am PDT

Software Development for 64-Bit RISC-V Processor Verification - Sreenadh S & Sangeetha N., Center for Development of Advanced Computing, India

A software model (Nigama) of 64-bit RISC-V IMAFD processor was developed in CPP language. Nigama is used as a reference model for verification of in-house developed out-of-order RV64IMAFD processor. The processor running on FPGA or simulation platform can be connected to Nigama through Ethernet interface and a test program runs on DUT and Nigama simultaneously in step lock mode and the result of each instruction on DUT is compared with that of Nigama and if there is any mismatch an error log is printed. This log is used further for debugging. This method is much faster even if larger test programs of more than 2 Billion instructions are running on DUT. This verification method has been successfully used for verifying the in-house developed 64-bit out-of-order single core RISC-V ISA based processor (RV64IMAFD) and enhancement of Nigama for multicore verification is under progress.

Speakers

Sreenadh S

Principal Engineer, Center for Development of Advanced Computing, India

Completed Graduation in Electronics and Telecommunication engineering.Started career as embedded software developer at Center for Development of Advanced Computing, India.Designed and developed various baremetal programs in assembly and C to verify in-house developed peripheral IP... Read More →

Sangeetha N.

Intern in Master of Technology, Center for Development of Advanced Computing, India

Completed Graduation in Electronics and Telecommunication engineering and Post graduation in VLSI design and embedded systems.Currently doing post graduation internship at Center for Development of Advanced Computing, India.Now involved in the project: Microprocessor Development Programme... Read More →

RISC V GlobalForum cdac sreenadh pdf

Thursday September 3, 2020 4:30am - 5:00am PDT
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Industry

4:45am PDT

ProtoCPU: Modelling an In-Order RISC-V Core in gem5 - Anuj Justus Rajappa, IIT Madras

Ideate, simulate, develop and repeat seems to be the general ideal workflow for any product development process, especially when stakes are high. ProtoCPU was born to fulfill this workflow by aiding in simulation of an in-order RISC-V processor designed by the SHAKTI team at IIT Madras. ProtoCPU is a 5 stage inorder core, designed in gem5 with a goal to cycle-accurately represent the C-class processors. It was built from scratch using the gem5 APIs. The model is under development and currently supports bare-metal full system RISCV simulations in gem5. The session brings in the overview of this model in gem5, merits and demerits of designing cpu models in gem5 along with the additional needs yet to be met to ease the job of microarchitectural design space exploration with respect to RISC-V ISA.

Speakers

Anuj Justus Rajappa

Project Associate, IIT Madras

J. Anuj is a Project Associate, working with SHAKTI team at IIT Madras. He secured 1st rank in both B.Sc. Physics from Loyola College (Autonomous), Chennai and M.Sc. Electronics from St.Joseph’s college (autonomous), Trichy, India with ‘Dr. A. P. J. Abdul Kalam Endowment Cash... Read More →

Thursday September 3, 2020 4:45am - 5:00am PDT
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Technical

5:05am PDT

Using Formal to Vaccinate RISC-V Designs Against Catastrophic Bugs - Dr. Ashish Darbari, AXIOMISE

Bug escapes in silicon lead to catastrophic failures – well-known being the Intel FDIV bug, Ariane 5 explosion, and several ongoing security vulnerabilities affecting almost all the computing devices.

Formal verification provides exhaustive proofs of bug absence, as well as efficient bug-hunting. The use of formal methods in chip designs prevents bugs to creep in ensuring the chips remain clean, not exhibiting any symptoms of bugs – almost the same way as humans react when they are vaccinated against life-threatening bugs.

So, is "formal verification" the vaccine that chip design needs to keep itself safe from bugs? Dr. Darbari believes it is. In this talk, he presents a methodology and an APP that can be used to find bugs both in designs-under-development and in pre-verified processors. The methodology shown is able to prove the bug absence using any formal verification tool.

Speakers

Dr. Ashish Darbari

Founder & CEO, AXIOMISE

Dr. Darbari is the founder & CEO of Axiomise - a company founded in London to democratize formal verification and make it easy for everyone to adopt formal methods for hardware verification. He has been actively using formal methods for over two decades. Before starting Axiomise... Read More →

Thursday September 3, 2020 5:05am - 5:35am PDT
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Technical

5:35am PDT

Ask the Expert Session with Florian Wohlrab, RISC-V Ambassador and Head of Sales EMEA & Japan, Andes Technology

Speakers

Florian Wohlrab

Head of Sales EMEA & Japan, Andes Technology

Florian Wohlrab is one of the first RISC-V Ambassadors and Head of Sales for EMEA and Japan at Andes Technology. His mission is to help bring RISC-V towards mainstream and enable others to easily get started within the RISC-V ecosystem. He is fascinated by the open, modular, compact... Read More →

Thursday September 3, 2020 5:35am - 6:05am PDT
MeetingPlay

Ask the Expert

5:35am PDT

Break

Thursday September 3, 2020 5:35am - 6:05am PDT
MeetingPlay

Break

6:05am PDT

BM-310 Small and Efficient MCU Core - Alexander Kozlov, CloudBEAR

In this talk, we will provide a detailed feature description of small and efficient microcontroller core BM-310 including supported extensions, pipeline options for performance/efficiency tradeoffs, memory subsystem, interrupt control, power management, and debug capabilities.

Speakers

Alexander Kozlov

CTO, CloudBEAR

Thursday September 3, 2020 6:05am - 6:35am PDT
MeetingPlay

Industry

6:05am PDT

Optimizing RISC-V Custom Instructions with Software Driven Analysis and Profiling - Duncan Graham & Simon Davidmann, Imperas Software

One of the attractive features of RISC-V is the ability to add, and with ecosystem support, new optimized instructions and extensions to a processor implementation. At first it appears as simple task to look at opportunities in the application code that could be accelerated with some dedicated new hardware. However, since hardware typically has a much longer life cycle than software, future updates and roadmap needs must be anticipated. Thus, the art of ISA design is using fine grain analysis to accelerate just the key steps while leaving sufficient flexibility to support new software updates and advances. While in multi-core arrays a custom extension can offer a lightweight communication channel between processors. This extends the scope beyond the processor itself into system design and analysis. This talk will illustrate the key profiling and analysis steps for custom extensions.

Speakers

Duncan Graham

Sr Applications Engineer, Imperas Software

Duncan covers developing and supporting the virtual platform tools & models, and project manager of the SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements). He has previously held Senior MTS & Apps Engineering roles with Elixent, FrontierSilicon,Tensilica... Read More →

Simon Davidmann

President & CEO, Imperas Software

Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) - the place for Fast Processor Models. Simon is also the chair of the Verification Task Group of the OpenHW Group... Read More →

Imperas Optimizing RISC V Custom Instructions Final pdf

Thursday September 3, 2020 6:05am - 6:35am PDT
MeetingPlay

Technical

6:40am PDT

Semidynamics New Family of High Bandwidth Vector-Capable Cores - Roger Espasa, SemiDynamics

In this session, SemiDynamics will disclose its new RISC-V application cores, targeted at bandwidth-hungry application domains such as Machine Learning, Recommendation Systems, Sparse Computation, HPC and Key-Value Stores. SemiDynamics will also open source its "Open Vector Interface (OVI)", a public spec that allows third-parties to design their own vector unit and connect it to SemiDynamics cores.

Speakers

Roger Espasa

CEO & Founder of Semidynamics, Semidynamics

Roger Espasa is the founder and CEO of Semidynamics, a European IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion TM misses, both targeted at HPC and Machine Learning. In addition, Semidynamics architected... Read More →

2020.07.24.Global Forum pdf

Thursday September 3, 2020 6:40am - 7:10am PDT
MeetingPlay

Industry

6:40am PDT

Trusted Execution State: An Extension for Lightweight Secure Function Calling - Mark Hill, Huawei Technologies R&D (UK) Ltd

Although Trusted Execution Environments (TEEs) can be built using the standard RISC-V machine mode as the trusted state this approach has some limitations:
- Machine mode must manage the lower privilege tasks, exceptions/interrupts and device drivers as well as managing secret data and providing trusted services. This dual use violates the security Principle of Least Privilege.
- Supporting all these mechanisms make the code large, increasing the risk of security loopholes appearing and providing more opportunity to create gadgets for ROP/JOP style attacks.
- Transitions between insecure and secure domains is inevitablly heavyweight as it must be syscall based.
This extension addresses these issues by adding a new Trusted Execution State which provides stronger protection and quicker handling of secret data.

Speakers

Mark Hill

Chief CPU Architect, Huawei Technologies R&D (UK) Ltd

Mark is Chief CPU Architect in the Device Chipset Department of Huawei's Consumer Business Unit. Since 2017 he has been involved in the architecture and design of all Huawei's RISC-V based MCUs covering a wide range of applications. Prior to joining Huawei he spent over 20 years at... Read More →

RISC V GlobalForum2020 Mark Hill pdf

Thursday September 3, 2020 6:40am - 7:10am PDT
MeetingPlay

Technical

7:10am PDT

Ask the Expert Session with Drew Fusitni, Linux Developer and Hardware Designer, and Olof Kindgren, Digital Design Engineer, Open Source Silicon expert, and RISC-V Ambassador, Qamcom

Speakers

Olof Kindgren

Sr Digital Design Engineer, Qamcom

Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations... Read More →

Drew Fustini

Linux Kernel Engineer, Tenstorrent

Drew Fustini is an open hardware designer and embedded Linux developer. He serves on the board of directors for the Open Source Hardware Association and the BeagleBoard.org Foundation, and is an ambassador for the RISC-V Foundation. Drew designs circuit boards for OSH Park, a PCB... Read More →

Thursday September 3, 2020 7:10am - 8:00am PDT
MeetingPlay

Ask the Expert

7:10am PDT

Break

Thursday September 3, 2020 7:10am - 8:00am PDT
MeetingPlay

Break

8:00am PDT

Keynote: Krste Asanovic, Chairman of the Board, RISC-V International

Speakers

Krste Asanovic

Chair, RISC-V International

Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded... Read More →

RISCV 20200825 StateOfUnion pdf

Thursday September 3, 2020 8:00am - 8:20am PDT
MeetingPlay

Keynote

8:25am PDT

Keynote: EPI, The European Approach for Exascale ages. The Road Toward Sovereignty - Jean-Marc Denis, Chair of the Board, European Processor Initiative

The European Commission has set an extremely ambitious target to the European Processor Initiative (EPI: developing the processor that will empower the European Exascale machines, and laid the foundations of the European Sovereignty for high-performance and low-power processing units based in RISC-V, the Opensource ISA. The European ambition and how it is implemented is presented. The possible roadblocks and issues are also explained.

Speakers

Jean-Marc Denis

Chief of Staff of the Innovation and Strategy Division at Atos, Chair of the Board of the European Processor Initiative (EPI), SiPearl

Since the beginning of 2020, Jean-Marc is the Chief of Staff of the Innovation and Strategy Division at Atos. In addition, since mid-2018, Jean-Marc has been also elected as Chair of the Board of the European Processor Initiative (EPI).Prior to that, Jean-Marc Denis took different... Read More →

EPI RISC V 2020 09 05 for export pdf

Thursday September 3, 2020 8:25am - 8:45am PDT
MeetingPlay

Keynote

8:50am PDT

Keynote: Chips Alliance: The Open Source Hardware Roadmap - Zvonimir Bandic, Chairman, CHIPS Alliance & Sr Director, Western Digital Corporation

The RISC-V open ISA has enabled a new generation of processing architectures. There now exists an open hardware group, CHIPS Alliance where organizations, non-profits, individuals, and academia can collaborate to solve the next generation of processing challenges. See the milestones that CHIPS Alliance has already accomplished and learn about our roadmap and future vision for open source hardware.

Speakers

Zvonimir Bandic

Senior Director, Western Digital

Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and... Read More →

Thursday September 3, 2020 8:50am - 9:00am PDT
MeetingPlay

Keynote

9:05am PDT

Keynote: NVIDIA’s secure RISC-V processor - Frans Sijstermans & Joe Xie, NVIDIA

Security is key to many of NVIDIA’s markets. Example applications are protecting video and gaming IP, keeping private data on shared servers from leaking, and safety of self-driving cars. NVRISCV is at the core of NVIDIA’s security architecture. It is a RISC-V core with closely coupled co-processors that incorporate many security features to protect against a variety of attacks. Some features are architectural and we are proposing those as RISC-V specifications; others are implementation specific. We believe that RISC-V is ideally positioned to standardize around a set of security specs and best practices, helped by transparency and joint development by the community, inherent to its open source nature.

Speakers

Frans Sijstermans

VP of Engineering, NVIDIA

Frans Sijstermans is a VP of hardware engineering managing NVIDIA’s multi-media hardware department. He is responsible for RISC-V, security and cryptography accelerators, a deep learning accelerator, and camera, video, and display processing HW. Frans also serves on the board of... Read More →

Joe Xie

Director of ASIC Hardware Engineering, nVidia Semiconductor Technology (Shanghai) co. ltd

Joe is a director in nVidia hardware department. Joe has over 15 years of experience in hardware security CPU architecture and design, he oversees a team of architects, designers and verification engineers working on nVidia RISC-V processor cores and various security IP blocks for... Read More →

Thursday September 3, 2020 9:05am - 9:20am PDT
MeetingPlay

Keynote

9:20am PDT

Ask the Expert Session with Krste Asanovic, Chairman, and Dave Patterson, Vice Chair, RISC-V International

Speakers

Krste Asanovic

Chair, RISC-V International

David Patterson

Vice Chair, RISC-V International

David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1976.Dave's research style is to identify critical questions for the IT industry and gather inter-disciplinary groups of... Read More →

Thursday September 3, 2020 9:20am - 9:45am PDT
MeetingPlay

Ask the Expert

9:20am PDT

Break

Thursday September 3, 2020 9:20am - 9:45am PDT
MeetingPlay

Break

9:45am PDT

The Case for RISC-V in Space - Gianluca Furano, European Space Agency

This paper presents preliminary position of the ESA on the use of the RISC-V ISA for onboard electronics in space. The modular nature of this ISA, the availability of a rich software ecosystem, a rapidly growing community and a pool of open-source IP cores will allow space industry to spin-in developments from terrestrial fields (in terms of security, artificial intelligence, support for operating systems, hardware acceleration etc.) while focusing its efforts mainly on aspects related to the specific needs of on-board electronics for space applications. The use of an open, non proprietary ISA, will allow ad-hoc design of microarchitecture-level soft error countermeasures that can greatly increase the robustness of ASIC and FPGA implementations.

Speakers

Gianluca Furano

On Board Computer Engineer, European Space Agency

Gianluca Furano, PhD, works in European Space Agency's Data System Division since 2003. He is in charge for research and development activities and he coordinates ESA activities on on-board artificial intelligence. Among Gianluca's interest in ESA are on-board computers and their... Read More →

RISC Slides pdf

Thursday September 3, 2020 9:45am - 10:00am PDT
MeetingPlay

Technical

9:45am PDT

Riscof - A Risc-V Compliance Framework and More - Neel Gala, InCore Semiconductors

An open and configurable ISA such as the RISC-V requires an equally open, agile and easily customizable compliance framework. There are significant challenges in building such a framework which accounts for : vast configurable options of RISC-V targets, choosing and integrating different reference models (formal, RTL, iss, silicon, etc), defining and extracting ISA driven functional coverage, a suite of tests and much more.

The proposed compliance framework, RISCOF, achieves some of the above goals through a robust and completely open-source (under permissive licences) python+yaml based framework. This talk will highlight the current status of RISCOF, its components, capabilities and how it can be extended to be more than just compliance.

Speakers

Neel Gala

CTO | Co-Founder, InCore Semiconductors

Neel is the CTO of InCore–an early stage fabless startup from India. Incore is one of the leading provider of RISC-V processor IP in India. Neel received his B-Tech from NIT-Warangal in ECE in year 2010. In 2012, Neel co-founded the SHAKTI processor program at IIT Madras, which... Read More →

RISCV GF 2020.pptx pdf

Thursday September 3, 2020 9:45am - 10:15am PDT
MeetingPlay

Technical

10:00am PDT

Noel-V: A New High-Performance RISC-V Processor Family - Johan Klockars & Alen Bardizbanyan, Cobham Gaisler AB

Cobham Gaisler AB has a long heritage in the space industry, with SPARC based LEON processors and GRLIB IP components. They provide both IP and space qualified chips.
The NOEL-V processor family, based on the RISC-V ISA, is a new addition to the Gaisler line. The first variant released, HPP64, is a 64-bit high-performance in-order dual-issue processor, capable of running Linux (other configurations under development). This variant has a 7-stage pipeline, can achieve 4.69 Coremark/MHz by initial estimates and supports RV64GCBNH (some extensions are under development).
The NOEL-V processors are open sourced under the GPL license. Fault tolerance and additional components for high performance, like L2-cache and a pipelined FPU, can be licensed commercially. The NOEL-V processors are embedded in Gaisler's GRLIB IP library, making it possible to build systems around them using GRLIB.

Speakers

Johan Klockars

Hardware Engineer, Cobham Gaisler AB

Johan Klockars has an MSc in Computer Science & Engineering and is a Hardware Engineer at Cobham Gaisler, working on their new RISC-V CPU core. He has been doing embedded systems development for 20 years: image processing and communications protocols in FPGAs, real-time systems, WiFi... Read More →

Alen Bardizbanyan

Hardware Engineer, Cobham Gaisler AB

Alen Bardizbanyan holds a PhD degree on VLSI and computer architecture. He has mainly worked with energy efficiency in processor architectures and involved in teaching activities for VLSI design during his PhD studies. During the last 4 years he has been working at Cobham Gaisler... Read More →

RV GF NOEL V pdf

Thursday September 3, 2020 10:00am - 10:15am PDT
MeetingPlay

Technical

10:20am PDT

Cloud-based Verification of Open Source RISC-V Cores Using the Metrics Cloud Platform and Codasip SweRV Support Package - Roddy Urquhart, Codasip & Dan Ganousis, Metrics Design Automation

Verification is crucial to processor core development, accounting for as much as 2/3 of the SoC/ASIC development cycle. A major advantage of the RISC-V ISA is users are allowed to modify the processor IP. However, if the processor IP is modified, verification is necessary and is solely the responsibility of the user. High code coverage as well as complete functional coverage is essential and techniques such as constrained random verification are necessary requiring considerable use of RTL simulators. The Metrics Cloud Platform exploits the massive parallelism and elastic storage available in the Cloud for big simulation jobs using a SystemVerilog/UVM methodology to enable the execution of parallel unlimited RTL simulations. This paper explains how the Codasip SSP enables users of open source SweRV Core to efficiently verify their processor IP in the Cloud using the Metrics Platform.

Speakers

Roddy Urquhart

Senior Director Marketing, Codasip

Dr Roddy Urquhart has worked in a number of roles in the semiconductor, EDA and semiconductor IP sectors. Roles have included: -Senior Director Marketing, Codasip 2020- -Managing Director, Flicq UK Ltd, 2018-2020 -Director European Development, Codasip 2017-2018 -Vice President Marketing... Read More →

Dan Ganousis

Vice President Sales & Marketing, Metrics Design Automation

Dan is a veteran of the semiconductor industry having held a variety of engineering, sales and marketing roles. Most recent roles have been: Vice President Sales and Marketing, Metrics Design Automation, 2020- Vice President Sales Strategic Accounts, SiFive, 2018-2020 Director of... Read More →

Joint paper Codasip Metrics 20200805a pdf

Thursday September 3, 2020 10:20am - 10:50am PDT
MeetingPlay

Technical

10:20am PDT

Verifying All the Flexibility of RISC-V within SoC DV Test Plans - Simon Davidmann & Lee Moore, Imperas Software

The open ISA of RISC-V permits may optional configurations and microarchitectural choices plus the options to add custom extensions. This provides designers and system architects freedom to explore optimized designs across almost all market segments. The verification challenge can be addressed with a number of approaches. This talk will give the latest updates to the RISC-V compliance test suite, which was developed with the free riscvOVPsim reference model, the use of an open source instruction stream generator and UVM methodologies based on a SystemVerilog encapsulated RISC-V reference model for step-and-compare verification efficiency. These techniques will be illustrated with results from testing some popular open source cores. This can be a guide to starting your next project with RISC-V, either testing the complete processor or custom extensions.

Speakers

Simon Davidmann

President & CEO, Imperas Software

Lee Moore

Sr. Consulting Engineer, Imperas Software Ltd.

Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently... Read More →

Imperas verifying all the flexibility of RISC V talk at Global Forum 2020 pdf

Thursday September 3, 2020 10:20am - 10:50am PDT
MeetingPlay

Technical

10:55am PDT

RISC-V True Random Number Generation: Probably Too Important to be Left to Chance - Markku-Juhani O. Saarinen, PQShield Ltd.

Crypto Task Group's proposed RISC-V True Random Number Generator (TRNG) architecture breaks with previous ISA TRNG practice by splitting the Entropy Source (ES) component away from cryptographic PRNGs into a separate interface, and in its use of polling. We describe the interface, its use in cryptography, and the rationale behind its engineering choices. This design is informed by lessons learned from earlier mainstream ISAs, recently introduced SP 800-90B and FIPS 140-3 entropy audit requirements, AIS 31 and Common Criteria, current and emerging cryptographic needs such as post-quantum cryptography. We also introduce Minidice, a minimalistic TRNG reference implementation that uses the Entropy Source together with RISC-V AES instructions.

Speakers

Markku-Juhani O. Saarinen

Staff Cryptography Engineer, PQShield Ltd.

Dr. Saarinen is a Staff Cryptography Architect at PQShield (Oxford, UK) and a Professor of Practice at Tampere University (Finland). Markku has worked as a cryptographer and security engineer for over 25 years. He joined PQShield at its inception as a University of Oxford spin-out... Read More →

r5gf2020 saarinen slides new pdf

Thursday September 3, 2020 10:55am - 11:25am PDT
MeetingPlay

Technical

11:25am PDT

Ask the Expert Session with Mark I Himelstein, RISC-V CTO, and Stephano Cetola, Technical Program Manager, RISC-V International

Speakers

Mark Himelstein

CTO, RISC-V International

Mark Himelstein is the CTO for RISC-V International. Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing product architecture, analysis, mentoring and interim management... Read More →

Thursday September 3, 2020 11:25am - 12:10pm PDT
MeetingPlay

Ask the Expert

11:25am PDT

Break

Thursday September 3, 2020 11:25am - 12:10pm PDT
MeetingPlay

Break

12:10pm PDT

Stay Ahead with the Latest Advances in RISC-V Development Tools - Shawn Prestridge, IAR Systems

Every developer needs their application to be fast, compact, and energy-friendly. Using a highly optimized compiler and a comprehensive debugger along with fully-integrated analysis tools will help you ensure the quality and efficiency of the code you are developing. We give you access to the complete set of build tools, code analysis and debugging tools from one feature-rich IDE, enabling you to speed up time-to-market and therefore spend your time on the innovative parts that will differentiate your product.

All developers have a lot to gain by having access to professional development tools with professional technical support from a long-term vendor they can rely on. This session is for anyone interested in learning more about the possibilities offered when using professional development tools.

Speakers

Shawn Prestridge

US Field Applications Engineer Team Manager, IAR Systems

Shawn Prestridge has served as Senior Field Application Engineer at IAR Systems since 2008. Shawn has worked in the software industry since 1993 and prior to joining IAR Systems he held the position of Embedded Hardware/Software Engineer with Texas Instruments as well as doing Embedded... Read More →

Thursday September 3, 2020 12:10pm - 12:40pm PDT
MeetingPlay

Industry

12:10pm PDT

Where Is the 32-Bit Glibc Port? - Alistair Francis, Western Digital

The process to upstream 32-bit RISC-V (RV32) has been going on for over two years now. This talk will cover why the process has taken so long, what is upstream and what still remains to be done.

This will hopefully be the first upstream architecture that is 32-bit but has a 64-bit time_t. This means that the architecture is y2038 safe and only works on the Linux kernel 5.4+.

This talk will cover the Y2038 Unix Epoch overflow problem and what is being done to fix it. It will describe how and why this applies to the 32-bit RISC-V glibc port.

Speakers

Alistair Francis

Technologist, WDC

Alistair Francis currently works at Western Digital as part of the RISC-V software research team. He is the QEMU RISC-V maintainer; developing, reviewing and merging QEMU patches. He also has a focus on security, specifically secure operating systems related to Root of Trust (RoT... Read More →

Thursday September 3, 2020 12:10pm - 12:40pm PDT
MeetingPlay

Technical

12:45pm PDT

An Automated Scalable RISC-V Cache Coherency Verification Project - Adnan Hamid, Breker Verification Systems, Inc.

As the RISC-V ISA is leveraged in more complex extended processors, maintaining cache coherency is becoming a significant factor. Verifying coherency across an SoC with a high degree of coverage is complex and time consuming. Working with RISC-V processor providers, including SiFive, Breker has developed a scalable solution that may be reapplied to different RISC-V processor configurations, that runs common cache coherency test techniques across a broad range of cases. Unique integration verification issues that occur due to the open nature of the RISC-V ISA, its extensibility, and some of the applications in which it is being applied have come to light. This presentation will share various approaches to cache coherency verification, how they may be adapted to unique RISC-V issues, and how this may be encapsulated for reusability across different RISC-V applications.

Speakers

Adnan Hamid

President & CTO, Breker Verification Systems, Inc.

After nearly 10 years of processor and system-level design for a startup in Oregon, Aileen moved to Synopsys, where she worked as a verification consultant for 19 years in the UK, San Diego, Copenhagen, and the Bay Area. She was involved in countless projects and worked to develop... Read More →

Thursday September 3, 2020 12:45pm - 1:15pm PDT
MeetingPlay

Technical

1:20pm PDT

CORE-V Verification Test Bench – Commercial Quality Verification of Open-Source RISC-V Cores - Rick O'Connor, OpenHW Group; Simon Davidmann, Imperas; Aimee Sutton, Metrics

High quality verification is crucial to any HW IP development and in particular for open-source processor cores. Industry quality, coverage driven verification is essential as is leveraging commercial tools, flows and simulators. These are "must haves" in order for open-source IP to be adopted by leading semiconductor companies for use in high volume SoCs. This talk provides details of the CORE-V Verification Test Bench, an open-source 'step & compare' System Verilog / UVM environment built by the OpenHW Group ecosystem leveraging the Imperas RISC-V Golden Reference Model and the Metrics Cloud-based EDA Platform.

Speakers

Aimee Sutton

Sr. Applications Engineer, Metrics Design Automation

Aimee has been working in design verification of microelectronics since she her days as a co-op student from the University of Waterloo. After working as a DV engineer and a DV consultant for over a decade, she joined Metrics as one of the original employees in 2016. Since then she... Read More →

Simon Davidmann

President & CEO, Imperas Software

Rick O’Connor

President & CEO, OpenHW Group

An industry executive with several years of semiconductor and system level experience, Rick is Founder, President & CEO of the OpenHW Group a not-for-profit, global organization with 100+ members & partners where developers collaborate on open-source cores, related IP, tools and software... Read More →

OpenHW CORE V Verif Test BenchV3 pdf

Thursday September 3, 2020 1:20pm - 1:50pm PDT
MeetingPlay

Industry

1:20pm PDT

Unlocking Javascript: V8 on RISC-V - Peng Wu & Brice Dobry, Futurewei Technologies

The absence of a JavaScript engine on RISC-V is an important gap in the RISC-V software ecosystem. This talk presents our efforts to develop a RISC-V backend for V8, the most popular JS engine today. I will provide an overview of the V8 architecture and get into some details about the target-specific parts that required the most porting effort. I discuss our porting strategy and the lessons that we have learned along the way. I will then share some demos of our working port, which currently passes 95%+ of V8 test cases and supports both JavaScript and WebAssembly. This V8 RISC-V port is an ongoing open-source effort. We will conclude the talk with the development roadmap and invite participation from community developers as well as early adopters.

Speakers

Peng Wu

Technical VP, Futurewei Technologies

Peng Wu is Technical VP for the Programming Technologies domain at Futurewei Technologies. Previously she founded and served as the head of the Programming Technologies Lab at Huawei, one of the first of its kind ina major Chinese company. Prior to that, she was a research staff member... Read More →

Brice Dobry

Principal Engineer, Futurewei Technologies

Brice Dobry is a Principal Engineer in the Programming Technologies Lab at Futurewei. Brice has been with Futurewei since 2009, when he joined to help pioneer the compiler team in the US and China. The team has expanded from compilers to a great variety of tooling, languages, and... Read More →

Thursday September 3, 2020 1:20pm - 1:50pm PDT
MeetingPlay

Technical

1:50pm PDT

Ask the Expert Session with Carlos Eduardo de Paula, Cloud Architect, Red Hat

Speakers

Carlos Eduardo de Paula

RISC-V Ambassador and Domain Architect, Red Hat

Carlos is a RISC-V Ambassador and works for Red Hat as a Cloud Architect designing solutions for customers and helping them into the cloud journey.He is currently creating ChiselV, a RISC-V processor written in Chisel HDL and writes about Kubernetes and containers on multiple architectures... Read More →

Thursday September 3, 2020 1:50pm - 2:20pm PDT
MeetingPlay

Ask the Expert

1:50pm PDT

Break

Thursday September 3, 2020 1:50pm - 2:20pm PDT
MeetingPlay

Break

2:20pm PDT

Code Size Compiler Optimizations and Techniques for Embedded Systems - Aditya Kumar, Facebook

Code size of embedded applications has been a growing concern recently. While storage becomes cheaper and smaller, developers find creative ways to increase code size by adding features or unnecessary software engineering. Compilers have come a long way in optimizing applications for code size. While most compiler optimization work were focused on application performance, we have seen increase in the code size optimizations in recent years.

In this presentation I'll talk about classical as well as recent compiler optimizations for code size, a few of which I implemented in the LLVM compiler. Some optimizations (hot cold splitting, function entry instrumentation) require collecting data at runtime. I'll provide an overview of how those compiler techniques help reduce code size. I'll also talk about some tips and techniques that help reduce binary size. I'll talk about both gcc and LLVM.

Speakers

Aditya Kumar

Software Engineer, Facebook

Aditya Kumar is a senior software engineer at Facebook and Distinguished speaker at ACM. He has been working on compiler toolchains (LLVM,Clang and GCC) since 2012. He has contributed optimizations like GVNHoist, Hot Cold Splitting, Hexagon specific optimizations to the LLVM compiler... Read More →

OSSEmbeddedLinuxConference pdf

Thursday September 3, 2020 2:20pm - 2:50pm PDT
MeetingPlay

Technical

2:55pm PDT

RVfpga: Using A Commercial RISC-V Processor to Teach Computer Architecture for the Next Generation of Engineers and Computer Scientists - Sarah L. Harris, University of Nevada, Las Vegas & Daniel A. Chaver Martinez, University Complutense of Madrid

RISC-V FPGA (RVfpga) provides a set of instructions, tools, and labs that shows how to target a commercial RISC-V system to an FPGA, add more functionality to the system, and analyze and modify the RISC-V core itself. RVfpga, which is being developed by Imagination Technologies and its academic and industry partners, includes a Getting Started Guide and labs that show how to build Chips Alliance’s SweRVolf SoC (based on Western Digital’s RISC-V SweRV EH1 core) in Xilinx’s Vivado and target it to an FPGA, write and debug C and assembly programs using PlatformIO, add more I/O capabilities such as 7-segment displays and SPI, I2C, or UART serial buses, and use timers and interrupts. A more advanced follow-on set of labs describes the RISC-V datapath, control, and memory hierarchy in detail and shows how to modify them to support custom instructions and new cache configurations and policies.

Speakers

Sarah Harris

Professor, University of Nevada in Las Vegas

Dr. Harris is a Professor at the University of Nevada, Las Vegas (UNLV) in the Electrical & Computer Engineering Department. She earned her M.S. and Ph.D. at Stanford University and has worked at Hewlett Packard, Nvidia, and the Technical University of Darmstadt. Before joining the... Read More →

Daniel A. Chaver Martinez

Associate Professor, University Complutense of Madrid

Daniel A. Chaver Martínez studied Physics at the University of Santiago de Compostela (USC) from 1994 to 1998 and Electrical Engineering at University Complutense of Madrid (UCM) from 1998 to 2000. He developed his PhD from 2000 to 2006 at UCM. He has taught many different courses... Read More →

RVfpga HarrisChaver RISC V GlobalForum2020 pdf

Thursday September 3, 2020 2:55pm - 3:10pm PDT
MeetingPlay

Technical

3:10pm PDT

Omnixtend Boot Protocol and Coherent Scaleout - Dejan Vucinic, Western Digital Corporation

Over the past eighteen months OmniXtend has become the de facto standard for building multi-socket RISC-V systems. Recent efforts within the Interconnects Workgroup in CHIPS Alliance resulted in the definition of an initialization and configuration protocol which enables the construction of massively parallel systems of arbitrary size. This is a simple yet race-free approach to setting up any number of coherent endpoints at boot. It enables different system models: a single instance of an operating system over several nodes with Non-Uniform Memory Access (NUMA) or independent instances of operating systems on different nodes sharing global memory coherently and peripherals non-coherently. This talk will cover the basics of the protocol and the currently enabled usage scenarios, as well as the future vision for fault-tolerance and coherent hotplug.

Speakers

Dejan Vucinic

Director, R&D Engineering, Western Digital Corporation

Dr. Dejan Vucinic is Director of R&D Engineering at Western Digital. His group's research interests include computational storage scaleout with RISC-V, OmniXtend and programmable network switches. He chairs the Interconnects Workgroup in CHIPS Alliance, a forum for discussion of open... Read More →

Thursday September 3, 2020 3:10pm - 3:25pm PDT
MeetingPlay

Industry

3:30pm PDT

Ask the Expert Session with Allen Baum, Senior Adult in the Room, Esperanto Technologies

Speakers

Allen Baum

Chair of RISC-V International Architecture Test SIG, Esperanto Technologies

Allen Baum, Esperanto Technologies System ArchitectI have been involved in computer architecture for 50 years, including working on processors for HP (HPPA), Apple, ARM, DEC StrongArm and Alpha, and Intel Xeon processors.

Thursday September 3, 2020 3:30pm - 3:55pm PDT
MeetingPlay

Ask the Expert

3:30pm PDT

Break

Thursday September 3, 2020 3:30pm - 3:55pm PDT
MeetingPlay

Break

4:00pm PDT

Keynote: The First Decade of RISC-V: A Worldwide Phenomenon - David Patterson, Vice Chair, RISC-V International

In this keynote, I first examine whether the center of the RISC-V universe is now Asia, Europe, or North America. Next is an overview of the RISC-V International Open Source Laboratory (RIOS Lab) and it’s open source PicoRio project, a Raspberry Pi-like small board computer based on RISC-V. I then explore how the open RISC-V architecture and related open source hardware and software projects affect geopolitical issues.
I conclude the talk with the premier of a video that celebrates the 10 year anniversary of RISC-V—it’s birthday was May 18, 2010—where key contributors review RISC-V’s first decade.

Speakers

David Patterson

Vice Chair, RISC-V International

RISC V Summit Keynote Patterson (1) pdf

Thursday September 3, 2020 4:00pm - 4:20pm PDT
MeetingPlay

Keynote

4:25pm PDT

Keynote: An Investor Perspective on RISC-V, The Opportunities and Challenges Ahead - Guru Chahal, Partner, Lightspeed Venture Partners

The market for CPUs has been dominated by an increasingly small number of companies in the last decade. One reason for this has been a closed, proprietary instruction set, which makes it very hard for customers to move to a new processor. RISC-V removes this major hurdle and opens up the processor market to more innovation and value creation. Lightspeed is a global, multi-stage, multi-sector venture capital firm. In this talk I'll dig a bit deeper into how we at Lightspeed are thinking about the opportunities and challenges ahead for RISC-V.

Speakers

Guru Chahal

Partner, Lightspeed Venture Partners

Guru Chahal is a partner at Lightspeed Venture Partners, a global, multi-stage venture capital firm. Guru focuses on early stage enterprise startups in cloud, security, DevOps, observability, and enterprise IT. He first joined the Lightspeed team in 2012 supporting Lightspeed investments... Read More →

Thursday September 3, 2020 4:25pm - 4:45pm PDT
MeetingPlay

Keynote

4:50pm PDT

Keynote: Information Revolution, Chips, and Openness - Shahin Khan, Founding Partner & Analyst, OrionX.net

Information Age, Chips, and Openness
This talk puts chips and the open source model in the context of Information Age: what enables it, the changes it causes and it demands, and the opportunities it opens up for semiconductor projects. It makes a case for openness as a non-negotiable required element of the digital revolution.

Speakers