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Thursday, September 3 • 1:20pm - 1:50pm
CORE-V Verification Test Bench – Commercial Quality Verification of Open-Source RISC-V Cores - Rick O'Connor, OpenHW Group; Simon Davidmann, Imperas; Aimee Sutton, Metrics

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High quality verification is crucial to any HW IP development and in particular for open-source processor cores. Industry quality, coverage driven verification is essential as is leveraging commercial tools, flows and simulators.  These are "must haves" in order for open-source IP to be adopted by leading semiconductor companies for use in high volume SoCs. This talk provides details of the CORE-V Verification Test Bench, an open-source 'step & compare' System Verilog / UVM environment built by the OpenHW Group ecosystem leveraging the Imperas RISC-V Golden Reference Model and the Metrics Cloud-based EDA Platform.

Speakers
avatar for Aimee Sutton

Aimee Sutton

Sr. Applications Engineer, Metrics Design Automation
Aimee has been working in design verification of microelectronics since she her days as a co-op student from the University of Waterloo. After working as a DV engineer and a DV consultant for over a decade, she joined Metrics as one of the original employees in 2016. Since then she... Read More →
avatar for Simon Davidmann

Simon Davidmann

CEO, Imperas Software
Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) - the place for Fast Processor Models. Simon is also the chair of the Verification Task Group of the OpenHW Group... Read More →
avatar for Rick O’Connor

Rick O’Connor

President & CEO, OpenHW Group
An industry executive with several years of semiconductor and system level experience, Rick is Founder, President & CEO of the OpenHW Group a not-for-profit, global organization with 100+ members & partners where developers collaborate on open-source cores, related IP, tools and software... Read More →



Thursday September 3, 2020 1:20pm - 1:50pm PDT
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