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Thursday, September 3 • 1:45am - 2:15am
Vector Compliance Testing for RISC-V - Hideki Sugimoto & Koji Adachi, NSITEXE Inc.

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The first step to testing a RISC-V vector instruction implementation is to test compliance to the specification. To do this requires both compliance tests and a reference model. NSITEXE, with its Data Flow Processor (DFP) IP block, required such testing for its implementation of the vector engine. The Imperas RISC-V ISS, riscvOVPsim, is in use as the reference model for the RISC-V Compliance Test Suite (CTS). Imperas has developed a Directed Compliance Test Generator, which achieves over 95% functional instruction coverage with those tests generated. Using the Vector CTS for the NSITEXE configuration has enabled confirmation of compliance with v0.8 of the RISC-V vector specification. This paper will discuss the NSITEXE DFP vector engine implementation, the generation of the Vector Compliance Tests for the NSITEXE configuration and the results of those tests including coverage data.


Hideki Sugimoto

Hideki Sugimoto is currently CTO of NSITEXE, Inc., a 100% subsidiary of DENSO Corporation, which is working to innovate embedded SoC architecture to makes it more generic, flexible and scalable. He has over 25 years of experience in NEC as a processor architect, designer and also... Read More →
avatar for Koji Adachi

Koji Adachi

Manager, NSITEXE, Inc.
Koji Adachi has more than 15 years of experience as a CPU architect and designer for embedded applications and is currently a CPU architect at NSITEXE, Inc. Previously, he worked on CPU ISA (Virtualization, Multithreading) and micro architecture design for Automotive MCUs. He also... Read More →

Thursday September 3, 2020 1:45am - 2:15am PDT