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Thursday, September 3 • 12:45pm - 1:15pm
An Automated Scalable RISC-V Cache Coherency Verification Project - Adnan Hamid, Breker Verification Systems, Inc.

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As the RISC-V ISA is leveraged in more complex extended processors, maintaining cache coherency is becoming a significant factor. Verifying coherency across an SoC with a high degree of coverage is complex and time consuming. Working with RISC-V processor providers, including SiFive, Breker has developed a scalable solution that may be reapplied to different RISC-V processor configurations, that runs common cache coherency test techniques across a broad range of cases. Unique integration verification issues that occur due to the open nature of the RISC-V ISA, its extensibility, and some of the applications in which it is being applied have come to light. This presentation will share various approaches to cache coherency verification, how they may be adapted to unique RISC-V issues, and how this may be encapsulated for reusability across different RISC-V applications.

avatar for Adnan Hamid

Adnan Hamid

President & CTO, Breker Verification Systems, Inc.
After nearly 10 years of processor and system-level design for a startup in Oregon, Aileen moved to Synopsys, where she worked as a verification consultant for 19 years in the UK, San Diego, Copenhagen, and the Bay Area. She was involved in countless projects and worked to develop... Read More →

Thursday September 3, 2020 12:45pm - 1:15pm PDT