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Thursday, September 3 • 6:05am - 6:35am
Optimizing RISC-V Custom Instructions with Software Driven Analysis and Profiling - Duncan Graham & Simon Davidmann, Imperas Software

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One of the attractive features of RISC-V is the ability to add, and with ecosystem support, new optimized instructions and extensions to a processor implementation. At first it appears as simple task to look at opportunities in the application code that could be accelerated with some dedicated new hardware. However, since hardware typically has a much longer life cycle than software, future updates and roadmap needs must be anticipated. Thus, the art of ISA design is using fine grain analysis to accelerate just the key steps while leaving sufficient flexibility to support new software updates and advances. While in multi-core arrays a custom extension can offer a lightweight communication channel between processors. This extends the scope beyond the processor itself into system design and analysis. This talk will illustrate the key profiling and analysis steps for custom extensions.

Speakers
DG

Duncan Graham

Sr Applications Engineer, Imperas Software
Duncan covers developing and supporting the virtual platform tools & models, and project manager of the SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements). He has previously held Senior MTS & Apps Engineering roles with Elixent, FrontierSilicon,Tensilica... Read More →
avatar for Simon Davidmann

Simon Davidmann

CEO, Imperas Software
Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) - the place for Fast Processor Models. Simon is also the chair of the Verification Task Group of the OpenHW Group... Read More →



Thursday September 3, 2020 6:05am - 6:35am PDT
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