RISC-V Global Forum 2020

Verification is crucial to processor core development, accounting for as much as 2/3 of the SoC/ASIC development cycle. A major advantage of the RISC-V ISA is users are allowed to modify the processor IP. However, if the processor IP is modified, verification is necessary and is solely the responsibility of the user. High code coverage as well as complete functional coverage is essential and techniques such as constrained random verification are necessary requiring considerable use of RTL simulators. The Metrics Cloud Platform exploits the massive parallelism and elastic storage available in the Cloud for big simulation jobs using a SystemVerilog/UVM methodology to enable the execution of parallel unlimited RTL simulations. This paper explains how the Codasip SSP enables users of open source SweRV Core to efficiently verify their processor IP in the Cloud using the Metrics Platform.