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Thursday, September 3 • 10:20am - 10:50am
Cloud-based Verification of Open Source RISC-V Cores Using the Metrics Cloud Platform and Codasip SweRV Support Package - Roddy Urquhart, Codasip & Dan Ganousis, Metrics Design Automation

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Verification is crucial to processor core development, accounting for as much as 2/3 of the SoC/ASIC development cycle. A major advantage of the RISC-V ISA is users are allowed to modify the processor IP. However, if the processor IP is modified, verification is necessary and is solely the responsibility of the user. High code coverage as well as complete functional coverage is essential and techniques such as constrained random verification are necessary requiring considerable use of RTL simulators. The Metrics Cloud Platform exploits the massive parallelism and elastic storage available in the Cloud for big simulation jobs using a SystemVerilog/UVM methodology to enable the execution of parallel unlimited RTL simulations. This paper explains how the Codasip SSP enables users of open source SweRV Core to efficiently verify their processor IP in the Cloud using the Metrics Platform.

Speakers
RU

Roddy Urquhart

Senior Director Marketing, Codasip
Dr Roddy Urquhart has worked in a number of roles in the semiconductor, EDA and semiconductor IP sectors. Roles have included: -Senior Director Marketing, Codasip 2020- -Managing Director, Flicq UK Ltd, 2018-2020 -Director European Development, Codasip 2017-2018 -Vice President Marketing... Read More →
DG

Dan Ganousis

Vice President Sales & Marketing, Metrics Design Automation
Dan is a veteran of the semiconductor industry having held a variety of engineering, sales and marketing roles. Most recent roles have been: Vice President Sales and Marketing, Metrics Design Automation, 2020- Vice President Sales Strategic Accounts, SiFive, 2018-2020 Director of... Read More →



Thursday September 3, 2020 10:20am - 10:50am PDT
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