RISC-V Global Forum 2020

Ideate, simulate, develop and repeat seems to be the general ideal workflow for any product development process, especially when stakes are high. ProtoCPU was born to fulfill this workflow by aiding in simulation of an in-order RISC-V processor designed by the SHAKTI team at IIT Madras. ProtoCPU is a 5 stage inorder core, designed in gem5 with a goal to cycle-accurately represent the C-class processors. It was built from scratch using the gem5 APIs. The model is under development and currently supports bare-metal full system RISCV simulations in gem5. The session brings in the overview of this model in gem5, merits and demerits of designing cpu models in gem5 along with the additional needs yet to be met to ease the job of microarchitectural design space exploration with respect to RISC-V ISA.