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Thursday, September 3 • 4:45am - 5:00am
ProtoCPU: Modelling an In-Order RISC-V Core in gem5 - Anuj Justus Rajappa, IIT Madras

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Ideate, simulate, develop and repeat seems to be the general ideal workflow for any product development process, especially when stakes are high. ProtoCPU was born to fulfill this workflow by aiding in simulation of an in-order RISC-V processor designed by the SHAKTI team at IIT Madras. ProtoCPU is a 5 stage inorder core, designed in gem5 with a goal to cycle-accurately represent the C-class processors. It was built from scratch using the gem5 APIs. The model is under development and currently supports bare-metal full system RISCV simulations in gem5. The session brings in the overview of this model in gem5, merits and demerits of designing cpu models in gem5 along with the additional needs yet to be met to ease the job of microarchitectural design space exploration with respect to RISC-V ISA.

avatar for Anuj Justus Rajappa

Anuj Justus Rajappa

Project Associate, IIT Madras
J. Anuj is a Project Associate, working with SHAKTI team at IIT Madras. He secured 1st rank in both B.Sc. Physics from Loyola College (Autonomous), Chennai and M.Sc. Electronics from St.Joseph’s college (autonomous), Trichy, India with ‘Dr. A. P. J. Abdul Kalam Endowment Cash... Read More →

Thursday September 3, 2020 4:45am - 5:00am PDT