RISC-V Global Forum 2020

RISC-V FPGA (RVfpga) provides a set of instructions, tools, and labs that shows how to target a commercial RISC-V system to an FPGA, add more functionality to the system, and analyze and modify the RISC-V core itself. RVfpga, which is being developed by Imagination Technologies and its academic and industry partners, includes a Getting Started Guide and labs that show how to build Chips Alliance’s SweRVolf SoC (based on Western Digital’s RISC-V SweRV EH1 core) in Xilinx’s Vivado and target it to an FPGA, write and debug C and assembly programs using PlatformIO, add more I/O capabilities such as 7-segment displays and SPI, I2C, or UART serial buses, and use timers and interrupts. A more advanced follow-on set of labs describes the RISC-V datapath, control, and memory hierarchy in detail and shows how to modify them to support custom instructions and new cache configurations and policies.