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Thursday, September 3 • 2:55pm - 3:10pm
RVfpga: Using A Commercial RISC-V Processor to Teach Computer Architecture for the Next Generation of Engineers and Computer Scientists - Sarah L. Harris, University of Nevada, Las Vegas & Daniel A. Chaver Martinez, University Complutense of Madrid

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RISC-V FPGA (RVfpga) provides a set of instructions, tools, and labs that shows how to target a commercial RISC-V system to an FPGA, add more functionality to the system, and analyze and modify the RISC-V core itself. RVfpga, which is being developed by Imagination Technologies and its academic and industry partners, includes a Getting Started Guide and labs that show how to build Chips Alliance’s SweRVolf SoC (based on Western Digital’s RISC-V SweRV EH1 core) in Xilinx’s Vivado and target it to an FPGA, write and debug C and assembly programs using PlatformIO, add more I/O capabilities such as 7-segment displays and SPI, I2C, or UART serial buses, and use timers and interrupts. A more advanced follow-on set of labs describes the RISC-V datapath, control, and memory hierarchy in detail and shows how to modify them to support custom instructions and new cache configurations and policies.


Sarah L. Harris

Associate Professor, University of Nevada, Las Vegas
Sarah L. Harris is an Associate Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas. She completed her B.S. at B.Y.U. and her M.S. and Ph.D. at Stanford University. Before joining UNLV in 2014, she was a faculty member at Harvey Mudd College from... Read More →

Daniel A. Chaver Martinez

Associate Professor, University Complutense of Madrid
Daniel A. Chaver Martínez studied Physics at the University of Santiago de Compostela (USC) from 1994 to 1998 and Electrical Engineering at University Complutense of Madrid (UCM) from 1998 to 2000. He developed his PhD from 2000 to 2006 at UCM. He has taught many different courses... Read More →

Thursday September 3, 2020 2:55pm - 3:10pm PDT