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Thursday, September 3 • 10:20am - 10:50am
Verifying All the Flexibility of RISC-V within SoC DV Test Plans - Simon Davidmann & Lee Moore, Imperas Software

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The open ISA of RISC-V permits may optional configurations and microarchitectural choices plus the options to add custom extensions. This provides designers and system architects freedom to explore optimized designs across almost all market segments. The verification challenge can be addressed with a number of approaches. This talk will give the latest updates to the RISC-V compliance test suite, which was developed with the free riscvOVPsim reference model, the use of an open source instruction stream generator and UVM methodologies based on a SystemVerilog encapsulated RISC-V reference model for step-and-compare verification efficiency. These techniques will be illustrated with results from testing some popular open source cores. This can be a guide to starting your next project with RISC-V, either testing the complete processor or custom extensions.

avatar for Simon Davidmann

Simon Davidmann

CEO, Imperas Software
Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) - the place for Fast Processor Models. Simon is also the chair of the Verification Task Group of the OpenHW Group... Read More →
avatar for Lee Moore

Lee Moore

Senior Applications Engineer, Imperas Software
Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Lee worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Lee is also a private pilot, and recently... Read More →

Thursday September 3, 2020 10:20am - 10:50am PDT