The "V" ISA extension for vector processing has been proposed to RISC-V to exploit data parallelism in domains such as machine learning and high-performance computing applications. In contrast to traditional SIMD processors with fixed-length vectors, the RISC-V vector extension defines a vector-length agnostic architecture where work is vectorized independently of a vector length that can be discovered at run-time. This is a departure from existing SIMD frameworks where the vector lengths are known statically, and a new intrinsic interface that takes advantage of scalable nature of RISC-V vectors is being developed by the community. This talk will provide an overview of the vector extension and how to program the vector processor, using Andes NX27V as an example, with C-level scalable vector types and intrinsic functions, as well as design choices and future evolution of the API.
Chih-Mao Chen is a software developer at Andes Technology, where he is responsible at developing RISC-V toolchain based on the LLVM compiler infrastructure.
