RISC-V Global Forum 2020

A software model (Nigama) of 64-bit RISC-V IMAFD processor was developed in CPP language. Nigama is used as a reference model for verification of in-house developed out-of-order RV64IMAFD processor. The processor running on FPGA or simulation platform can be connected to Nigama through Ethernet interface and a test program runs on DUT and Nigama simultaneously in step lock mode and the result of each instruction on DUT is compared with that of Nigama and if there is any mismatch an error log is printed. This log is used further for debugging. This method is much faster even if larger test programs of more than 2 Billion instructions are running on DUT. This verification method has been successfully used for verifying the in-house developed 64-bit out-of-order single core RISC-V ISA based processor (RV64IMAFD) and enhancement of Nigama for multicore verification is under progress.